1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing metallic interconnects.
2. Description of the Related Art
As the level of integration of integrated circuit devices increases, the number of devices in a silicon chip increases and hence the number of interconnects necessary for linking semiconductor devices also increases. Consequently, integrated circuits, in particular metallic interconnects, are becoming harder to manufacture. In fact, how to produce quality conductive lines with ideal operating properties within the confines of a small contact area is a goal that all semiconductor manufacturers are actively pursuing.
Due to a reduction of line width through miniaturization, current density sustained by each metallic line increases correspondingly. Passing a high current through a narrow conventional aluminum metal line results in electromigration and subsequently leads to a device reliability problem.
To reduce electromigration, especially for sub-micron devices, copper is a better choice of material than aluminum for forming interconnects. Copper has a low resistivity and a higher resistance to electromigration. Moreover, a copper layer can be deposited by chemical vapor deposition or electroplating. However, copper is also highly resistant towards most conventional gaseous etchants, and hence copper lines are difficult to produce by conventional methods. Typically, copper lines are usually manufactured by a dual damascene process.
FIGS. 1A through 1C are schematic cross-sectional views showing the progression of steps in a conventional dual damascene process.
As shown in FIG. 1A, a substrate having a copper line 102 therein is provided. A top surface 102a of the copper line 102 is exposed. An inter-metal dielectric layer 104 is formed over the substrate 100. The inter-metal dielectric layer 104 is formed, for example, by sequentially depositing a silicon oxide, a silicon nitride and a silicon oxide layer over the substrate 100. Silicon oxide and silicon nitride have different etching rates with respect to an etchant. Silicon nitride may also be deposited over the substrate 100 to form a silicon nitride layer prior (not shown) to the formation of the inter-metal dielectric layer 104. This has the advantage of preventing copper atoms from diffusing into the inter-metal dielectric layer 104 leading to device malfunction or undesired bridging between metallic interconnects.
As shown in FIG. 1B, a dual damascene opening consisting of a trench 106 and a contact opening 110 is formed in the inter-metal dielectric layer 104 with the contact opening 110 located under the trench 106. To form the dual damascene opening, a patterned photoresist layer (not shown) is formed over the inter-metal dielectric layer 104. The inter-metal-dielectric layer 104 is etched using the patterned photoresist as an etching mask and the silicon nitride layer as an etching stop layer. Hence, the trench 106 is first formed in the inter-metal dielectric layer 104. The patterned photoresist layer is removed, and then another patterned photoresist layer 108 is formed over the inter-metal dielectric layer 104. Using the patterned photoresist layer 108 as a mask, the inter-metal dielectric layer 104 is etched again to form the contact opening 110 that exposes the surface 102a of the copper line 102.
As shown in FIG. 1C, the photoresist layer 108 is removed by ashing using oxygen plasma. The plasma ashing is carried out at a high temperature with oxygen flowing at a rate of about 2000 to 3000 sccm. Oxygen plasma oxidizes organic molecules inside the photoresist material, which contains carbon (C), hydrogen (H), nitrogen (N) and oxygen (O), into gaseous carbon dioxide (CO2), water (H2O) and nitrogen oxides (NOx). The resulting gaseous products including carbon dioxide, water and nitrogen oxide are pumped away. High temperature is used to facilitate the oxidation of the photoresist material and accelerate photoresist removal.
Typically, the ashing chamber for removing photoresist material is raised to a temperature of about 250xc2x0 C. However, at such a high temperature, the exposed surface 102a of the copper line 102 is also attacked by oxygen plasma. A portion of the copper near the surface 102a is oxidized into loose cupric oxide (Cu2O) or copper oxide (CuO). Hence, electrical conductivity of the copper line decreases and contact resistance at the contact opening increases.
Although the oxides of copper can be dissolved in an alkali solvent, voids 112 are often formed on the surface 102a of the copper line 102. When a barrier layer and a seed layer are subsequently formed over the exposed sidewalls of the trench 106 and the contact opening 110, these voids 112 will result in a highly irregular profile. The irregular profile creates a high stress in subsequently deposited seeding layer during high temperature annealing, and may lead to an open contact due to surface tension. In a subsequent copper electroplating or copperless electroplating process, no copper adheres to the area where there is a break in the seeding layer. Hence, copper will not grow evenly inside the dual damascene opening, and a high contact resistance will result.
The invention provides a dual damascene process. A substrate having a copper line therein is provided. An inter-metal dielectric layer is formed over the substrate and the copper line. A patterned photoresist layer is formed over the inter-metal dielectric layer. The inter-metal dielectric layer is etched to from a contact opening and a trench that exposes a portion of the copper line with the contact opening located under the trench. At a low temperature and using N2H2 (H2:4%)/O2 as a gaseous mixture for producing a plasma, the photoresist layer is removed. Due to the presence of oxygen plasma, a surface layer of copper on the copper line is oxidized into copper oxide. Using the N2H2 (H2:4%) as a gaseous source, the copper oxide layer on the surface of the copper line is reduced back into copper. A barrier layer conformal to the trench and contact opening profile is formed. Copper is deposited to form a conformal first copper layer over the trench and the contact opening. Using the first copper layer as a seeding layer, a copper or a copperless electroplating is carried out to form a second copper layer. The second copper plug layer includes a trench line and a contact.
This invention also provides a dual damascene process that uses a gaseous mixture N2H2 (H2:4%)/O2 to produce a plasma for removing photoresist material at a low temperature so that the oxidation of copper on the surface of copper lines is greatly reduced.
This invention also provides a dual damascene process that uses a gas N2H2 (H2:4%) to reduce the copper oxide formed after the removal of photoresist material back into copper so that lowering of electrical conductivity of metallic interconnects and increase of contact resistance are prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.